As smaller transistors are manufactured, the critical dimension (CD) or resolution of patterned features is becoming more challenging to produce. Self-aligned patterning needs to replace overlay-driven patterning so that cost-effective scaling can continue even after EUV introduction. Patterning options that enable reduced variability, extend scaling and enhanced CD and process control are needed. Selective deposition of thin films such as void-less filing of recessed features is a key step in patterning in highly scaled technology nodes. However it's extremely challenging to fill retrograde recessed features with a material without creating a void in the material.
Silicon dioxide (SiO2) is the most common dielectric material in silicon microelectronic devices. However, despite its importance, void-less and seamfree filling of fine recessed features with SiO2 material has proved difficult at low temperatures.